Networking Cores
The integration of Ethernet Switches on FPGA is simplifying the communication between heterogeneous systems and applications. Thanks to the flexibility of reconfigurable devices combined with networking IPs, the end-equipment embeds not only Ethernet end-point capabilities but added-value switching features as well. In addition, the low latency of SoC-e IPs implemented over a non-blocking matrix infrastructure is a robust base for networking in critical systems. IEEE 1588-2008 is also supported and even the P2P mode of operation is implemented by hardware. This feature ensures port scalability and simplifies the integration of the IP. SoC-e has developed a portfolio of Ethernet Switching IPs focused on different applications and sectors. Thus, it is feasible combining the features of different IPs to obtain an optimal solution for each case.
| Available Models | Description |
|---|---|
| HSR/PRP Switch IP | This IP implements bumpless Ethernet connectivity ensuring zero-delay recovery time in case of network failure and no-frame lost. |
| Managed Redundant Switch (MRS) IP | The ManagedRedundantSwitch IP core is a combination of SoC-e HSR-PRPSwitch (HPS) and ManagedEthernetSwitch (MES) IP cores offering a redundant Ethernet switch capability. |
| Managed Ethernet Switch (MES) IP | The Managed Ethernet Switch IP core features a non-blocking crossbar matrix that allows continuous transfers between all the ports. |
| Unmanaged Ethernet Switch (UES) IP | The Unmanaged Ethernet Switch IP core (UES) implements a plug-and-play Ethernet switch on reconfigurable devices. |
| Multiport TSN Switch (MTSN) IP | The MTSN switch core provides precise time synchronization of network nodes to a reference time. |