MultiSync Core

MultiSync I/O Diagram

Overview

The MultiSync IP Core is a multi-protocol redundant time synchronization core that provides sub-microsecond time synchronization, providing maximum flexibility for every scenario. It is able to provide time synchronization using IEEE 1588-2008 (PTPv2) and IRIG-B time synchronization protocols.

 

Key Features

MultiSync Core Features

  • Multi-protocol redundant time synchronization.
  • IEEE 1588-2008 (PTPv2) and IRIG-B time synchronization protocols supported simultaneously.
  • 12 different operation modes.
  • 3 independent 64-bit adjustable timers associated to each slave. (32 bit sub-nanosecond frequency adjust.
  • One Pulse Per Second Output available.
  • Event timestamping supported (up to 4 different events simultaneously).
  • Alarm detection supported (up to 4 different alarms simultaneously).

The MultiSync IP Core supports the following synchronization input and output sources:

  • PTP: Ethernet. PTP Slave at the input/output
  • IRIG-B: IRIG-B Compliant signal. IRIG-B at the input/output
  • Free Running Timer: Digital input/output

This versatility enables different cases-of-use for MultiSync that are complementary:

  • It can provide time synchronization redundancy, making it possible to connect the IP to a PTP network and to an IRIG-B master at the same time. The user is able to select which is the time source used between the three available (PTP, IRIG-B, or free running timer)
  • It can act as a PTP to IRIG-B or IRIG-B to PTP bridge while the IP is synchronized with the selected master
  • It can act as a PTP or IRIG-B grandmaster

MultiSync can be sued in combination with SoC-e HSR-PRP switch, TSN Switch, Unmanaged Ethernet Switch, or Managed Ethernet Switch IP cores to introduce Ethernet traffic switching capabilities or HSR and PRP redundancy.

PTP Features

  • 10/100/1000 Mbps Ethernet operation supported
  • AXI-S interface supported:
    • 1 Gigabit Ethernet: 8-bit data width
    • 10 Gigabit Ethernet: 64-bit data width
    • Selection if the Ethernet frame includes the preamble or not
  • 16 position FIFO depth. Old timestamp values are stored for avoiding overrun
  • End-to-End and Peer-to-Peer delay mechanisms support
  • Support for PTP on both Layer 2 (Ethernet) and 3 (IPv4) interfaces
  • Support VLAN tagged PTP messages
  • IEEE 1588 Profiles: Default, Power, Power-Utility (IEC61850-9-3), AS

IRIG-B Slave Features

  • Support for DCLS and AM modulations
  • Internal filtering of the AM signal
  • Support for all IRIG-B coded expressions, including year information, control functions and straight binary seconds
  • IEEE 1344 extension support
  • Input type (IRIG-B time code) configurable both before implementation and on the fly
  • Implements a generic ADC controller compatible with SPI, QSPI and MICROWIRE protocols

IRIG-B Master Features

  • Support for DCLS and AM modulations
  • Support for all IRIG-B coded expressions, including year information, control functions and straight binary seconds
  • IEEE 1344 extension support
  • Input type (IRIG-B time code) configurable both before implementation and on the fly
  • Implements a generic ADC controller compatible with SPI, QSPI and MICROWIRE protocols

Free Running Timer Features

  • Fully managed by the user (time and frequency adjustment)

    Supported FPGAs

    • 6-Series (Spartan, Virtex)
    • 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
    • Ultrascale (Kintex, Virtex)
    • Ultrascale+ (Zynq MPSoC, Kintex, Virtex)

    Embedded Development Suite

    A hardware development platform is available. Latest documentation, design support files, reference design source files and tools are available for download free of charge.

    * Device supported by the free Xilinx Vivado WebPACK tool.

    Pricing, Availability and Ordering

    • Concurrent EDA is the US Distributor for SoC-e.
    • Currently Available to US customers only.
    • Please email Ray at This email address is being protected from spambots. You need JavaScript enabled to view it. with questions / quotes / orders.