MRS Switch Core

SoC-e MRS Switch block diagram



The ManagedRedundantSwitch IP core is a combination of SoC-e HSR-PRPSwitch (HPS) and ManagedEthernetSwitch (MES) IP cores offering a redundant Ethernet switch capability. The MES module is a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements Store&Forward switching approach in order to full Ethernet standard policy regarding frame integrity checking each frame before forwarding them. On the other hand, the HPS module introduces HSR and PRP redundant capabilities in the ports that are required. HSR switching approach is Cut-Through.

Thus, the combination of MES and HPS offers the maximum performance and maximum compatibility with the standards.

Key Features


  • Full-duplex 10/100/1000 Mbps Ethernet Interfaces
  • Half-duplex 10/100 Mbps Ethernet Interfaces
  • Full-duplex 10 Gbps Ethernet Interfaces (Under Development)
  • Configurable 3 to 16 Ethernet ports
  • MII/RMII/GMII/RGMII/SGMII/QSGMII Physical Layer device (PHY) interfaces
  • Different data rate supported for each port
  • Copper and Fiber optic media interfaces: 10/100/1000Base-T, 100Base-FX, 1000Base-X


  • Dynamic MAC Table with automatic MAC addresses learning and aging (up to 2048 entries)
  • Static MAC Table (up to 2048 entries)
  • Jumbo Frame Management
  • Ethertype Based Switching
  • Ingress Port Mirroring
  • Broadcast/Multicast Storm Protection
  • Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)

Time Synchronization

  • IEEE 1588v2 Stateless Transparent Clock functionality (P2P – Layer 2/ E2E – Layer 2)


  • RSTP (Software stack required)
    • Hardware support for RSTP
    • Reference RSTP stack for Linux provided with the IP Core
    • Posix Compatible RSTP stack available
  • MRP (Software stack not required)
    • Ring Manager (MRM)
    • Ring Client (MRC)
  • DLR (Software stack not required)
    • Beacon Based Node
    • Supervisor Node
  • HSR (Software stack not required)
    • Edition 3.0 (Latest)
    • Supported HSR modes: H, N, T, U, X
  • PRP (Software stack not required)
    • Edition 3.0 (Latest)
    • Supported PRP modes: Duplicates Discard, Duplicates Accept


  • MDIO, UART, AXI4-Lite or CoE (Configuration-over-ethernet) management interfaces
  • Configuration-over-Ethernet (COE): Full access to internal registers through the same Ethernet link that connects to the CPU
  • Drivers are provided with IP Core purchase
MRS I/O Diagram

Supported FPGAs

  • 6-Series (Spartan, Virtex)
  • 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
  • Ultrascale (Kintex, Virtex)
  • Ultrascale+ (Zynq MPSoC, Kintex, Virtex)

Embedded Development Suite

A hardware development platform is available. Latest documentation, design support files, reference design source files and tools are available for download free of charge.

* Device supported by the free Xilinx Vivado WebPACK tool.

Pricing, Availability and Ordering

  • Concurrent EDA is the US Distributor for SoC-e.
  • Currently Available to US customers only.
  • Please email Ray at This email address is being protected from spambots. You need JavaScript enabled to view it. with questions / quotes / orders.